Arteris, Inc. (AIP) Business

Item 1. Business

Overview

We are a leading provider of semiconductor system IP, including interconnect and other intellectual property (collectively, System IP) technology. Our System IP technology manages on-chip communications and IP block deployments by helping to enable the underlying data movement across chiplets, single-die and multi-die System-on-Chip (SoC) semiconductors. Our leading proprietary System IP solutions achieve this by connecting various semiconductor IP blocks such as processors, memory and logic via multiple Network-on-Chips (NoCs) in order for our customers to meet functional design goals as well as performance and power requirements, while addressing design complexity with efficient and lower cost solutions.

Founded in 2003, we are among the pioneers in the development of NoC IP technology for on-chip communication that addresses the growing complexity, performance, and cost requirements of SoC semiconductors and as a result, we have emerged as a global leader. Over time, we have expanded and scaled our interconnect IP and other IP businesses to provide hardware, software, documentation, support, and training under a license, support and maintenance fee and a royalty business model, to companies that design and produce semiconductors. In addition, we are finding an increasing number of customers further down the supply chain, such as system-level companies and original equipment manufacturers (OEMs). Our SoC integration automation capabilities were significantly enhanced by our acquisitions of Magillem in 2020, Semifore in 2022 and Cycuity in 2026, complementing our interconnect IP solutions by helping to automate the customer configuration of its NoC IPs, the process of integrating and assembling all of the customer’s IP blocks into SoC hardware, and ensuring correct hardware-software integration for software development. Products incorporating our IP are used to carry important data inside today’s complex SoCs across a broad range of applications, including aerospace and defense, automotive, communications, consumer electronics, enterprise computing, and industrial markets. Our interconnect IP solutions can be found in multiple industry-standard designs supporting instruction set architectures such as x86, Arm, RISC-V, CEVA, Synopsys ARC, Cadence Tensilica and MIPS, as well as memory controllers, UCIe, BoW, and XSR controllers, I/O and a variety of IP subsystems, to enable customers to integrate such IP blocks with high levels of efficiency and performance. Our solutions enable customer innovation because they are configurable for each customer’s design flow and SoC development projects and have wide applicability for many types of SoCs. We estimate that our solutions have been incorporated into over four billion production SoCs since inception.

Growing demand for our products and solutions is being driven by increasing SoC sophistication and associated complexity, now extending into disaggregation of SoCs into systems that implement the communication protocol aspects and partnering with industry-leading providers like Arm, Cadence, Synopsys, and others to help realize advanced systems. For example, traditional on-chip communication methods, including bus and crossbar interconnect IPs, are generally inadequate in handling modern semiconductor communications, and even more so for sophisticated applications or more complex chiplet designs. Technological advancements have led to increasingly complex SoCs that integrate numerous functions into a single semiconductor device. Massive amounts of wires, challenging timing closure, and routing congestion lead to greater die area and chip cost. Increased transistor density and design frequencies create higher power consumption leading to heat dissipation challenges and shorter battery life for electronic devices. These challenges have significantly complicated SoC innovation and contributed to the increasing adoption of System IP, across the numerous customer design starts coupled with the expanding number of NoC IPs used in current SoC.

We leveraged our extensive technical expertise to develop configurable IP for a new method for on-chip communication, the NoC, that has emerged over the past couple of decades to address these critical semiconductor development challenges. We accomplished this by pioneering the use of proprietary networking techniques for on-chip communications to remove the inherent architectural limitations of traditional on-chip communications, thereby improving ease of integration, performance, silicon area, and power consumption. In doing so, we enable our customers to achieve their design goals faster, more efficiently, and at lower costs. In addition, our SoC Integration Automation software solutions enable easier IP integration of our interconnect IPs – among other IP blocks that make up an SoC, across both hardware and software.

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We work directly with our customers throughout the SoC development process and seek to develop long-term, sustainable relationships with them as our technology becomes embedded in their products. We have historically maintained average customer retention rates of approximately 90%, reflecting the long-term nature of our customer relationships. Increasingly, we are also seeing system companies and even their customers becoming directly involved in SoC and NoC specifications and design, further expanding our ability to partner in this growing market. We also leverage our long history in interconnect IP designs and are able to serve a broad range of applications and deliver application and customer-specific features to our customers. For example, we are a leader in the market of interconnect for advanced driver assistance systems (ADAS) SoCs, which we believe is a result of our quality, reliability, and innovative technology targeted at that business application, and longstanding collaboration with automotive semiconductor companies, Tier 1 suppliers, and car manufacturing OEMs.

We provide solutions for the global chiplet and SoC market and believe that market growth will be driven by an increasing number of SoC designs and growing complexity, increasing average selling prices of interconnect IP and SoC Integration Automation software products. More specifically, we believe our growth will continue to be driven by technology trends requiring more advanced sophisticated on-chip data movement in the aerospace and defense, automotive, communications, consumer electronics, enterprise computing, and industrial markets. Also, the need for sophisticated system IP products is growing rapidly to address the requirements of chiplets and multi-die systems, lower power consumption, and higher operation frequency, smaller die size, and the ability to limited chip design expert resources to scale design needs in a cost-effective manner. As a result, we believe these trends have led to an increased economic benefit of in-licensing commercial semiconductor design IP and increased use of supported Electronic Design Automation (EDA) software a trend that we expect to continue.

For the years ended December 31, 2025, and 2024, we generated $70.6 million and $57.7 million in revenue, $6.7 million in cash flows provided by operating activities and $0.7 million in cash flows used in operating activities, and $34.7 million and $33.6 million in net loss, respectively. We expect to incur further net losses in the short term as we invest in our business. As of December 31, 2025, we had Annual Contract Value (ACV), which we define for an individual customer agreement as the total fixed fees under the agreement divided by the number of years in the agreement term, of $77.0 million. ACV plus royalties reached $83.6 million as of December 31, 2025.

Industry Background

The semiconductor industry is characterized by rapid technological change and increasing levels of integration. The semiconductor industry moved from integrated circuits that process data to SoCs that make decisions, and now extends to systems. SoCs grew more complex, enabling applications such as automated driving and enterprise computing data center acceleration. Integration of processors, accelerators, machine learning subsystems, sophisticated multi-channel memories, and an ever-larger number of interface standards has increased the need to move data efficiently inside the SoC and between SoC chiplets.

Increasing chip design complexity leads to rising costs. The move to more advanced process nodes has led to significantly more expensive and complex chip design methods and manufacturing processes.

Increasing chiplet and SoC complexity leads to increasing System IP value while also placing pressure on IP block assembly and connectivity efforts. As chiplets and SoCs grow in size, partly due to machine learning subsystems, communication complexity increases. The increasing use of coherent and non-coherent traffic in a single chiplet or SoC may amplify demand for our System IP products. Increased SoC complexity also requires SoC teams to manage potentially hundreds of IP blocks and chiplets from various vendors and internal development groups. These teams and their electronic design software (EDA) groups must implement IP supply chains with increasingly capable SoC integration automation to succeed, supported by standards like IEEE 1685 IP-XACT. As these standards become increasingly sophisticated with each generation, more sophisticated software is required to support them.

Rising demand from emerging end markets and new market participants is increasing the need for System IP products. New applications in markets such as aerospace and defense, automotive, communications, consumer electronics, enterprise computing, and industrial have increased the diversity and overall demand in the semiconductor market. These new applications, which often include more AI technology, safety, or complex hardware-software integrations, have led to an increase in the number and complexity of chiplet and SoC designs. Chips used for AI training and inference acceleration have increased in size, with added design complexities and performance requirements, leading to higher design costs.

There is a shift to third-party IP due to cost benefits, product differentiation, and accelerated time to market. Developing state-of-the-art SoC interconnect IP solutions is difficult, time-consuming and expensive. We believe this dynamic is accelerating the degree to which interconnect IP solutions are outsourced to commercial vendors. Commercial silicon proven interconnect vendors, such as Arteris, can potentially accelerate time-to-market by engaging with a greater variety of SoC applications and designs than the typical internal interconnect teams.

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Artificial Intelligence (AI) and Generative AI are transforming the semiconductor industry, revolutionizing how our customers approach design, development, and the resulting products. The rapid expansion of AI applications across various industries, combined with the increasing complexity of electronic system design, is accelerating the use of network-on-chip technologies. Moreover, it is also accelerating the broader shift from single-die to multi-die SoCs, increasing the numbers of NoCs being used in complex chiplets and SoCs.

System IP Market

SoC-type semiconductors consist of pre-made IP blocks that are either licensed from third parties by semiconductor and electronics companies or developed in-house. These IP blocks must be assembled into chiplets or SoCs as efficiently as possible to address semiconductor company and system OEM customer requirements. Many of these IP blocks, including processors and other functional blocks, such as machine learning and vision subsystems, perform processing functions and execute complex software stacks. These IP blocks can number in the hundreds on a single chip and generate and consume commands and data, as well as work together as a unit. As SoCs become more complex, there has emerged a class of silicon IP and software tools designed to assemble these IP blocks into a functioning SoC at target cost and performance. We call this the System IP market as it is focuses on high-performing, safe, secure and error free data movement throughout an SoC. The System IP market consists of NoC interconnect IP, NoC interface IP and SoC Integration Automation solutions. As SoC technology evolves, we believe that there is a significant opportunity for us to increase our value by introducing additional functionality for our customers to integrate their SoCs efficiently using our System IP solutions.

The addition of more processors, channels of memory access, additional I/Os interface standards, safety and security logic, and other subsystems within SoCs is driving the need for more advanced System IP, including NoC interconnect IPs. We believe this increase in SoC complexity has created a significant opportunity for sophisticated System IP products and solutions that incorporate NoC interconnect IP, NoC interface IP and SoC Integration Automation software.

Our market penetration spans multiple segments and customer adoption is most pronounced in the aerospace and defense, automotive, communications across wired and wireless, consumer electronics, enterprise computing, and industrial markets, driven by a higher rate of disruptive innovations.

Aerospace and Defense

The aerospace and defense sector, including government-sponsored programs, is undergoing a technology transition toward more highly integrated, software-defined systems. Increasing use of autonomy, multi-sensor processing, AI acceleration, and secure communications across air, space, land, and cyber environments is driving a shift from discrete components and field programmable gate arrays (FPGAs) to complex SoCs and application-specific integrated circuits (ASICs). In parallel, governments and defense agencies are emphasizing technological independence and supply chain resilience through domestic semiconductor initiatives. In addition, growth in commercial space, advanced avionics, and next-generation radar and electronic defense systems is further increasing system complexity and performance requirements. Our NoC and System IP technologies enable developers to meet these rigorous requirements with scalable, deterministic interconnect architectures.

Automotive Applications

The automotive market continues to undergo technology disruption with the advent of autonomous driving, electrification, electronic control unit consolidation, software defined vehicles and vehicle connectivity to the internet. Furthermore, cars are becoming increasingly connected to a large network of data centers, roadside and city infrastructures, and other vehicles, creating the “Internet of Cars”.

Due to the complex requirements of electronically enabled vehicles and the high rate of innovation required to compete in the “Internet of Cars” revolution, industry players are designing SoCs tailored to their sophisticated software and applications. This will result in more complex automotive-targeted SoCs, which we expect will continue to grow demand for reliable, configurable, and proven interconnect technologies that accelerate a product’s time to market while reducing overall costs.

Communications Applications

The wireless communications market is in the midst of disruption as 5G becomes more prevalent. 5G enables smart devices utilizing sophisticated SoCs to communicate more information at faster speeds while using less power. As 5G is adopted as the wireless market standard, it is expected to revolutionize markets, including cars and smart city vehicle infrastructure, factory automation, logistics, and consumer and business broadband.

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Already approaching the next generation network infrastructure, the industry has started the development of a roadmap towards 6G technology to be rolled out towards the end of this decade, with various 5G Advanced steps in-between.

We believe the transition to 5G and 6G, accelerated by AI demands, will result in further stringent requirements for bandwidth, latency, and power consumption, making an easy-to-integrate, high performance and low power on-chip interconnect a critical requirement.

Consumer Electronics Applications

Consumer electronics are trending towards being smaller, lighter, and more portable, while consumers expect simultaneously increased functionality and performance. Power consumption and heat management are increasingly critical as devices become smaller and more powerful, and consumers demand devices with longer battery life that do not overheat.

AI is also reshaping consumer electronics silicon designs, especially in smart home, gaming, and other connected devices.

From smartphones to wearables, AI-infused tables and laptops, gaming consoles, AR/VR innovation, smart TVs and smart home, the rate of recent innovation has significantly increased, pushing underlying silicon from what used to be relatively simple towards more sophisticated architectures which can benefit from System IP such as the technology provided by Arteris.

Enterprise Computing Applications

Large-scale AI cloud data centers are augmenting and replacing corporate data centers. This evolution expands the market size and value for AI GPUs and other XPUs used in them, enterprise solid-state storage systems and high-bandwidth memories, and the custom ASICs that control them, further strengthening demand for interconnect technologies that improve overall throughput, bandwidth, storage performance and provide data integrity. In addition, enterprise hyperscale computing companies are now creating proprietary multi-die SoCs and accelerators for their own products and data centers. We believe that these new entrants into semiconductor design will further accelerate market opportunities for third-party System IP products, including those from Arteris.

Some of the key areas for workload specific acceleration in data centers are AI, database processing, video/audio transcoding, and scientific computing. AI SoCs and computing pods must be “trained” on large data sets that have to be collected from real-world data utilizing “training” SoCs. A different class of AI SoCs uses such data to match the training data against actual data collected by sensors of the system utilizing “inference” SoCs. Whether used for training or inference, System IP technology deployment by companies like Arteris is on the rise in enterprise computing.

Industry Challenges

Interconnect IP development is a challenging, time-consuming, and expensive process. The need for robust, maintainable interconnect technology becomes increasingly important as chip designs become more complex and larger in size, both driven by advances in semiconductor manufacturing technology. Key interconnect IP development requirements and challenges include:

■Deep technical expertise and knowledge. Interconnect development requires an interdisciplinary engineering team with expertise and skill sets across a wide-range of engineering and scientific domains including hardware architecture, design, verification, EDA-class software development, and SystemC modeling, as well as deep understanding of physical design, design methodologies and networking architectures. The design process requires expertise in developing advanced hardware architectures to handle data coherency and consistency across the interconnect to achieve a high-performance, low power implementation. The design process requires expertise in developing advanced hardware architectures, engineers that have an awareness of the physical implementation and floorplan of the target chip in order to generate an architecture that meets SoC requirements and in-depth knowledge of graph theory, common interface protocols, data models, and graphical user interfaces.

■High quality. Interconnect IP requires a systematic deployment of quality-oriented methodologies, as any customer-level problems in the interconnect will result in SoC project delays or even project failures. Engineering teams creating interconnects must invest heavily not only in skilled engineering resources to develop and verify but also processes and methodologies that provide early indication of any potential quality issues.

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■Safety standards. High reliability of the interconnect is a heightened requirement for mission-critical markets including automotive, aerospace and defense, and industrial for robotics, medical and other applications.

■Long time commitment and high investment cost. We believe the engineering development cycle for each new interconnect and the market development cycle to establish a significant market position for a customer or for a commercial vendor requires large teams, many years and great expense. Additionally, we believe the investment required by a customer to internally create a configurable interconnect technology for a new SoC can be very expensive compared to the cost of licensing from a proven interconnect IP provider.

■Breadth of System IP products. With the need to address cache coherent, non-coherent, machine learning and chiplet traffic, customers need a System IP solution that works together across all these data traffic types. SoC integration automation technologies allow customers to manage the deployment of the rest of the IP blocks in the SoC in order to ease SoC IP integration. Meeting such requirements requires significant enterprise scale in engineering and customer support. Necessity for such combined technologies amounts to a significant barrier to entry in terms of time, cost and customer adoption.

Given the above requirements and challenges, developing commercial interconnect IP and software tools requires large engineering teams with advanced skill sets, significant amounts of time, and substantial financial investment. By licensing commercial interconnect IP, companies can free up resources to focus on developing new product capabilities and differentiators. Further, we believe the large investments needed to develop commercial interconnect IP also create barriers to entry for potential commercial competitors.

Our Solutions and Competitive Strengths

We are a leading provider of interconnect and other IP technology that manages the on-chip communications in SoC semiconductor devices. We believe our System IP is integral to our customers in aerospace and defense, automotive, communications across wired and wireless applications, consumer electronics, enterprise computing, and industrial markets. Our core strengths include:

■We help to enable the underlying data movement at the core of semiconductors. Network-on-Chip technology provides the core data transport layer between hundreds and thousands of IP blocks in today’s SoC devices or chiplets. Our technology connects the various XPUs, such as CPUs, GPUs, NPUs, TPUs, DPUs, IPUs, and MCUs.

■We help accelerate our customers’ time to market. Our interconnect IP software and SoC Integration Automation software solutions help accelerate SoC development at several different steps in the design cycle. For example, we offer design exploration and modeling capability, and we have automated test bench generation to accelerate the verification of our interconnect IP products. Our System IP product lines are structured so that our customers can customize the interconnect for their needs, helping accelerate interconnect IP customization for their particular SoC configurations. In addition to interconnect IP productivity features, we offer a combination of automated interconnect configuration software, pre-verified interfaces to IP block protocols, pre-verified interfaces to EDA tools and a pre-verified interconnect IP element library for rapid generation of customer-specific interconnect IP products. Our SoC Integration Automation software solutions also help accelerate SoC development by enabling the IP blocks making up an SoC to be packaged in a standard format called IP-XACT (Institute of Electrical and Electronics Engineers—IEEE 1685), which provides a uniform IP block assembly and reuse methodology. Our SoC Integration Automation software tool suite includes numerous packages that allow the configuration of IP block exit port registers, establish high-level SoC connectivity and link documentation to the IP-XACT design information.

■Our products help improve the performance and security of our customers’ SoCs. We believe that using our System IP products can result in improved SoC metrics such as higher performance, lower power consumption and smaller die area. We have extensive low-power management features such as three levels of clock gating and power domain features for low-power applications such as smartphone application processors and other SoCs for hand-held applications. We enable customers to partition their designs into “frequency domains”, allowing some domains to run at higher frequencies than others, in order to trade off performance against SoC power consumption.

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■We enable lower customer research and development and SoC unit costs. We believe that we enable lower chip research and development costs, lower SoC unit costs and reduce project risk as compared to solutions developed internally or licensed from another vendor. We have targeted our interconnect IP to be area-efficient so that we can offer silicon area savings, and resulting chip and chiplet cost savings, compared to other interconnect IP alternatives. We provide an integrated package of software, hardware, documentation, verification tools and pre-verified interfaces to major IP blocks and EDA tools. We believe our IP and software can save our customers time and money and enable them to focus on product differentiation and revenue generation.

■We believe we have grown our product portfolio through robust and focused research and development. Developing commercial interconnect IP and software tooling requires large and specialized engineering teams, significant amounts of time and extensive periods of commercial productization. We believe we have been the pioneer of using networking technology for on-chip communications and have been licensing such interconnect IP products since 2006. Our strategy is to deliver continuous innovation across both Interconnect IP and SoC Integration Automation software, with at least one major new product or major technology addition each year, and we have done so since 2013. As of December 31, 2025, we have 170 development engineers on staff covering IP hardware, software, verification, testing and methodology development. Such a sizable, multi-disciplinary engineering team allows us to undertake System IP products of sizable scale and permits us to work on multiple product development projects at the same time.

■We have grown our solutions through targeted acquisitions. We believe we have the ability to complement our product development with selective acquisitions to strengthen our System IP product portfolio. With our acquisition of Magillem in 2020, Semifore in 2022 and Cycuity in 2026, we added complementary technology that helps automate the process of integrating and assembling all of the customers’ IP blocks into chiplets, SoC, and its hardware-software integration to accelerate end product system development, as well as providing our customers hardware security verification solutions.

■We are able to address mission critical applications. We believe we are positioned to take advantage of the rapid growth of semiconductor content in cars. We have been focused on the automotive market since inception. Additionally, we have established customer relationships with market leaders such as Mobileye, Renesas, Socionext, NXP, BMW, Bosch, and many others. As cars continue to grow in complexity and connectivity, we believe there will be significant growth in the number of chiplets and increasingly complex SoCs that will need automotive grade on-chip interconnect IP. Our interconnect IP is designed to meet the automotive safety integrity level D (ASIL D) of the ISO 26262 automotive functional safety standard, which is the highest level, helping to position us as an ideal partner to innovative companies in the advanced automotive SoC market. We believe our solutions make it easier for our automotive semiconductor Tier 1 and OEM customers to collaborate and meet functional safety standards by establishing traceability between requirements, specifications, hardware and software implementation, verification and testing, and quality assurance. Because of this, our SoC Integration Automation software solutions are a complement to our interconnect IP in helping our customers meet their ISO 26262 functional safety requirements. Recently, our System IP and its resilience features have also seen increasing adoption for space exploration related applications.

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■With the acquisition of Cycuity, we are looking to help our customers reduce cybersecurity risks in microelectronics. With the acquisition of Cycuity, a leading provider and domain expert of semiconductor security verification technology, we are now working to help semiconductor and system companies developing chips and chiplets to mitigate hardware chip-level security risks. Semiconductor security vulnerabilities can result in compromised systems exposing critical information. Reported new Common Vulnerabilities and Exposures in hardware grew by over 15 times between 2020 and 2025, according to the data from US Department of Commerce’s National Institute of Standards and Technology. Additionally, the number of sophisticated cyberattacks continues to increase, targeting the vast amounts of unsecured data moving through semiconductors, from AI data centers, networks to a wide range of edge devices across the interconnect digital ecosystem. Moreover, the number of cybersecurity standards, regulations, policies and guidelines that our customers must adhere to for their IP, chiplet and chip designs is growing. Consequently, the establishment of robust hardware security assurance processes are paramount to safeguard not only the interests of manufacturers but also the privacy and security of end-users. In this dynamic landscape, semiconductor manufacturing security standards and compliance requirements are an integral aspect of chip design, development, and market viability and we believe our new security offering can provide meaningful solutions.

■We have developed a “Connected by Arteris” ecosystem to provide a broad set of System IP products. Interconnect IP is the data movement backbone of the SoC, connecting IP blocks such as CPUs, GPUs and memory controllers. We work with suppliers who provide these blocks, including IP companies such as Arm, SiFive, MIPS, Synopsys, Cadence Design Systems, Semidynamics, Andes, Codasip and other RISC-V IP vendors to support their products and protocols working with our SoC Integration Automation software and interconnect IP products. By offering an unbiased, standards-based interconnect infrastructure to which other IP vendors can connect, and supporting a broad range of transaction protocols, we believe we have simplified the industry’s development of heterogeneous SoCs while solidifying our role as a neutral, technology-agnostic provider across the semiconductor industry. In addition to on-chip integrations with partners, we work with EDA companies such as Synopsys, Cadence and Siemens to provide prepackaged interfaces to their EDA tools such as simulators, modeling systems, and logic and physical synthesis tools. By working closely with semiconductor IP and EDA leaders, some of whom compete with each other, we believe we have established credibility as a trusted enabler for the integration of their products within our joint customers’ chips and design flows.

■We believe we benefit from distinct competitive advantages. We believe our interconnect IP technology benefits from barriers to entry due to our many years of experience and the strength of our proprietary solutions, as well as the significant technical expertise and research costs required to develop a competitive product. We were founded in 2003 when we believe we helped pioneer the industry’s NoC interconnect IP and have maintained our competitive position with our global team of 170 hardware and software engineers as of December 31, 2025. Developing interconnect IP requires an interdisciplinary engineering team with expertise and skill sets across a wide range of sciences and domains as well as a deep understanding of semiconductor physical design, design methodologies, and networking architectures. Building such teams and keeping them together over long periods of time presents a challenge for many companies. Additionally, strategic patience and focus are required to participate in the market. For example, we believe that the customer acquisition process has a typical duration of two to nine months; following this, a customer’s chip design cycle is typically between one to three years. Customers typically start shipping their products containing our interconnect IP solutions between one to five years following completion of their product design, known as mass production at which point we start to receive royalties; this lasts for up to seven years or longer depending on the particular market. We also leverage our long history of interconnect IP design to deliver customer-specific features, further deepening our relationship and integration with the customer’s product. With our System IP products embedded in our customers’ SoCs, there are significant switching costs in moving to alternative solutions. We believe that our product quality and technical strength have enabled our high customer retention rate.

■We offer global support for our System IP customers. Interconnect IP technology is complex, and our customer support is critical for the successful deployment of our IP in our customers’ designs. We support customers utilizing our interconnect IP solutions on a global basis with architectural reviews, training, implementation support, and tape-out support. We work directly with our customers throughout their design processes to develop long-term sustainable relationships as our technology becomes embedded in their products. Many of our application engineers have advanced degrees, years of SoC design experience and passion for helping our customers drive their SoC designs to production status. We believe our application engineers are critical advisors to our customers’ design teams and offer competitive value to our customer’s silicon projects.

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Our Growth Strategy

We believe that as SoCs become more numerous and complex, the value of System IP technology increases since it enables the efficient movement of data within the ever-growing number of SoCs. We also believe that, as SoCs become more complex, interconnect IP technology becomes more time-consuming and riskier to develop internally within semiconductor and system companies, favoring System IP products provided by outside parties such as Arteris. As a dedicated interconnect IP provider, we enable our customers to leverage the knowledge and deep expertise developed by us through many years of focus on solutions for a variety of customers.

Our growth strategy includes the following:

■Leverage our System IP technology leadership and focused research and development to provide solutions for the semiconductor industry that designs and builds complex SoCs.

■Address high-growth markets, including aerospace and defense, automotive, communications across wired and wireless, consumer electronics, enterprise computing, industrial and AI/ML markets.

■Expand our customer base through ongoing System IP innovation.

■Expand our customer base through increased investment in sales and marketing.

■Continue to pursue selective acquisitions and other strategic transactions, such as joint ventures, to acquire complementary solutions and accelerate growth.

NoC Interface IP Growth Opportunity

NoC IP carries the majority of the data in an SoC. As a result, there is an opportunity to add additional customer value by developing additional data plane and control plane capabilities that attach directly to our interconnect IPs and are implemented in SoCs by our IP software. Currently, we offer NoC interface IP products such as a memory scheduler, last-level cache, SoC data observability and SoC debug IPs. We see an opportunity to further expand our product portfolio and market with additional control networks and subsystems that can accelerate our customers’ ability to deliver production SoCs to their end markets. Such networks may include clocking, register management and interrupt networks. Control subsystems such as power management, security, performance monitoring and debug may provide additional value to customers looking to lower the cost and risk of SoC development. With the integration of interconnect IP and NoC interface IPs, we believe we would be able to provide end-to-end solutions for quality of service, system level security and SoC resilience. NoC interface IP represents a natural expansion of our technical and business capabilities.

Our Solutions

We provide semiconductor interconnect IP and SoC Integration Automation software solutions to serve our target end-markets, including automotive, communications across wired and wireless, consumer electronics, enterprise computing, and industrial markets including robotics. We regularly release new products to address the rapid evolution of SoC technology. In 2025 we announced the release of an innovative new non-coherent NoC IP product FlexGen, which is a next-generation product that builds upon the silicon-proven and physically aware FlexNoC expertise to automate the creation of high-performance network-on-chip designs. Our two core product platforms are as follows:

a.Network-on-Chip IP Products

i.Non-coherent NoC IP, with FlexGen, FlexNoC and FlexWay

ii.Cache-coherent NoC IP, with Ncore

iii.NoC interface IP, with CodaCache

b.SoC Integration Automation Software Solutions Products

i.Hardware and software integration automation software, with Magillem Registers and CSRCompiler

ii.SoC assembly software, with Magillem Connectivity

c.Hardware Security Verification Software Products

i.Hardware security verification simulation for IP, sub-system, and SoCs, with Cycuity Radix-S

ii.Hardware security verification emulation for system-level SoC and firmware, with Cycuity Radix-M

iii.Static security analyzer, with Cycuity Radix-ST

In addition to historical annual introductions of new System IP products, we regularly develop and deliver updates that provide product enhancements to our customers. We believe the combination of our solutions and the strategic neutrality that we offer to the semiconductor industry positions us well as a reliable, trusted and innovative System IP solution for our customers.

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Network-on-Chip IP Products

We believe we offer the semiconductor industry an industry-leading commercially available interconnect IP portfolio.

Our commercially available NoC interconnect IP products are shipping in billions of devices worldwide across chiplets, multi-die SoCs, ASICs, MCUs and FPGA silicon designs. Innovative use of proprietary networking techniques for on-chip communications has enabled our industry-proven solutions to deliver higher chiplet and SoC performance with shorter design schedules, lower research and development costs, lower single-die and multi-die SoC unit costs, and reduced project risk when compared to customer-developed internal solutions. Select offerings of our semiconductor IP product portfolio include:

■FlexGen, FlexNoC and FlexWay: Silicon-proven, interconnect IP products that have been integrated into hundreds of chip designs. The underlying NoC technology converts on-chip communication signals between IP blocks, such as reads from and writes to memory, into digital packets. Packetizing on-chip communications allows the interconnect to be configured for enhanced performance and simplifies the connections of on-chip IP blocks, similar to how the internet eases the simultaneous connectivity of large numbers of computing devices. FlexWay is targeted at simpler SoC while FlexNoC targets the mainstream application. We also provide optional add-on packages for FlexNoC and FlexWay, such as the resilience package, which provide on-chip data protection that enables customers to meet the ISO 26262 and IEC functional safety standards for markets like automotive, and a large design performance package that addresses highly scalable peer-to-peer on-chip communications required by large SoCs such as those which include machine learning neural networks. FlexNoC and FlexWay started shipping in 2011 and we estimate that our solutions have been incorporated into over four billion production SoCs since inception. Our most recently announced product, FlexGen smart NoC IP, builds upon the silicon-proven and physically aware FlexNoC IP to automate the creation of high-performance NoC designs. Supported by AI-driven automation, FlexGen reduces manual iteration providing expert-level NoC topologies, while reducing wire-length and power which are critical to advance node designs and becoming increasingly valued. We believe these advancements are critical to meet the increasing computing demands of advanced technologies like AI, autonomous driving and cloud computing.

■Ncore: Silicon-proven, cache coherent interconnect IP product that provides scalable, configurable, and area-efficient features for use across multiple end markets. In an SoC, cache coherency is a special data traffic class that requires a corresponding coherent interconnect IP to manage it. In a multiprocessor system using shared memory, each processor has a local cache memory for efficiency, however, it is possible to end up with many copies of shared data in the system. One copy of the data may be in the main memory, whilst other copies may exist in one or more of the processor cache memories. When one of the copies of data is changed, the rest must also reflect that change. Ncore assists the timely propagation of data changes across the SoC in order to maintain cache coherency. Ncore is also more scalable and area-efficient than mesh-based interconnects and is optimized for heterogeneous cache coherent systems and offers multiple configurable snoop filters, multiple configurable proxy caches, and a modular, distributed architecture to provide system architects with the most advanced technology and more degrees of freedom to innovate. Since the initial shipment in 2016, we have launched multiple releases of Ncore which have been designed into various production SoCs for aerospace and defense, automotive, consumer electronics, enterprise computing and industrial markets. In 2022 we also entered into an Arm automotive agreement, with Arm as the processor IP provider and Arteris as interconnect IP provider for automotive microcontrollers (MCU) and SoCs to service growing customer needs. In 2023 Ncore achieved ISO 26262 certification up to ASIL-D, the most stringent level of functional automotive safety. In 2025 we announced expansion of our multi-die solution, delivering foundational technology for rapid chiplet-based innovation.

■CodaCache: CodaCache is a silicon-proven, last-level cache (or local memory) semiconductor IP product, used anywhere in the network-on-chip, for minimization of SoC data latency or improvement of performance. Frequent DRAM accesses waste clock cycles and causes performance to drop. CodaCache keeps data closer to the access point and lowers costs in certain SoC architectures. Design teams and architects can easily configure CodaCache based on area, timing, and other requirements. CodaCache provides the most flexibility of any commercial on-chip last-level cache IP, from setting associativity up to 16 ways, to configuring cache sizes and multiple target ports.

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SoC Integration Automation Software Solutions

We provide a suite of SoC Integration Automation software solutions that enables the packaging, reuse and integration of most types of IP blocks using the IP-XACT (IEEE 1685) standard. This SoC Integration Automation software suite of products from Magillem and Semifore acquisitions provides a design environment to any semiconductor and system company from the architecture of the SoC through the delivery of a fully documented and traceable chip design. This software suite manages the assembly of multiple IP blocks into SoC devices, registers configurations of IP blocks, and links design parameters and metadata to documentation. Our SoC Integration Automation software solutions are designed to shorten our customers’ design schedules and improve SoC engineers’ productivity across architects, logic designers, software/firmware developers, verification teams, and documentation teams. Arteris products provide a broad suite of software front-end design capabilities that can accelerate SoC development by providing highly configurable and scalable solutions. Our solutions address packaging, connectivity, register configuration, embedded software, and design software flows and we believe we provide best-in-class front-end design environments based on worldwide IEEE 1685 IP-XACT extensible markup language (XML) standard and SystemRDL language through our ready-made design solutions.

We believe the combination of SoC Integration Automation software solutions and SoC interconnect hardware provides our customers with more comprehensive SoC integration capabilities. Our SoC Integration Automation software technology suite across Magillem and CSRCompiler products cover the following key capabilities for SoC integration automation and overall SoC development acceleration:

■Magillem Connectivity: The Magillem connectivity product shortens and streamlines the system-on-chip (SoC) integration process. Magillem Connectivity allows users to build very complex, correct-by-construction SoC designs. IPs are packaged by the tool using the widely supported IP-XACT standard and can be configured and instantiated to create an SoC design in a single environment whilst ensuring design-data consistency. Magillem Connectivity uses built-in checkers to help automate time-consuming tasks, resulting in efficient and safe design updates or even restructuring of large sections of the design.

■Magillem Registers and CSRCompiler: The combination of Magillem and CSRCompiler products addresses hardware-software integration challenges for SoCs, where complex software algorithms control a growing array of specialized processors and hardware accelerators to deliver a robust semiconductor. The hardware/software interface (HSI) provides the technology for software to control this SoC hardware and it forms the foundation of the entire SoC design project. The Magillem Register product and CSRCompiler products automate the creation of this SoC foundation.

As mentioned above, critical tools in our SoC Integration Automation software product portfolio have been “Tool Confidence Level” (TCL) - certified by the TUV Sud to confirm that they are safe to use in mission-critical markets like automotive, aerospace and defense, and industrial.

Hardware Security Verification Software Products

We provide a suite of hardware security verification software solutions that bring a systematic approach to hardware security verification by helping customers explore and visualize how information flows through IP, sub-systems, and systems to identify security weaknesses, define measurable security requirements, and assess their effectiveness. This can help customers to discover potential security vulnerabilities in semiconductors during the design phase and to make sign-off decisions based on data and reports.

Our comprehensive products and solutions help customers deliver secure semiconductor products with:

■Cycuity Radix-S: Radix-S product is used during design creation and verification to detect and remediate security issues in IP blocks and subsystems of an SoC. The Radix-S information flow analysis features help customers identify the root cause of potentially serious security issues and systematically monitor and verify the effectiveness of their protection mechanisms.

■Cycuity Radix-M: Radix-M product extends the security verification performed with Radix-S to SoC system-level. It enables security verification to be performed while executing production firmware and software on the hardware system resulting in comprehensive system level security verification.

■Cycuity Radix-ST: Radix-ST is a static security analyzer designed to identify potential design weaknesses early in the development lifecycle without requiring simulation or emulation. Radix-ST performs analysis of Register Transfer Level designs and helps to identify hardware security weaknesses that exist in the design.

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Customers

We license our products to a global and diverse customer base, including semiconductor manufacturers, OEMs, hyperscale system houses, semiconductor design houses and other producers of electronic systems. We work directly with our customers throughout their design processes and seek to develop long-term, sustainable relationships with them as our technology becomes embedded in their products. As a result, we believe we are well positioned to continue to attract and retain customers, and to continue developing next-generation System IP products for their future products.

In 2025, we had one customer that represented more than 10% of our revenue.

During the fiscal year 2025, our revenue by geographic area based on customer location was as follows:

■41.5% of our revenue was derived from customers based in the Americas;

■10.9% of our revenue was derived from customers based in Europe and the Middle East; and

■47.6% of our revenue was derived from customers based in the Asia Pacific region.

Sales and Marketing

We work closely with our customers throughout the SoC design lifecycle to help them use our System IP solutions and products to meet their specific needs. It is important to our success that we engage our customers early and collaborate throughout the design cycle. Our support organization is able to communicate the best practices in SoC design practices and receive early insight into customer requirements. This insight often results in new and innovative product features.

System IP sales cycles range from six to twelve months or longer. For repeat customers, our sales cycle length is generally shorter.

As of December 31, 2025, we maintained sales offices, sales personnel, or sales representatives in the United States, China, France, South Korea, Japan, and Israel. As of December 31, 2025, our sales management had an average of 27 years of sales experience. As of December 31, 2025, we had 55 corporate and field application engineers. Corporate and field application engineers work closely with our customers in both presales and support roles, providing expert advice to our SoC architect and engineering users on how best to use our IP and software to design and implement their SoCs. As a result of these close relationships and detailed information sharing, our application engineers gather early knowledge of future expected customer needs including potential new sales opportunities within the customer and requirements for new capabilities for our products. Therefore, we believe our close relationships and technical credibility with our customers provide a competitive advantage.

Our marketing strategy emphasizes thought leadership and educates potential customers about how our products can address their System IP challenges. We use technical papers and in-person and online events, to highlight our capabilities.

Research and Development

We devote most of our operating expense to research and development of interconnect IP and SoC Integration Automation software solutions. The development of interconnect IPs for complex SoCs is a challenging task that requires multiple competencies and close contact with customers in order to deliver sophisticated solutions. The development and maintenance of these solutions require:

■Management of an interdisciplinary engineering team with expertise and skill set across a wide range of sciences and domains such as architecture, design, design verification, EDA-class software development, and SystemC modeling, as well as deep understanding of physical design, design methodologies and networking architectures;

■Advanced SoC architectures for handling data coherency and consistency that result in a high-performance implementation with low power;

■Complex design flows and methodologies, as well as specialized languages for generating configurable interconnect IP. The designs require configuration using thousands of parameters that must be meticulously managed with millions of combinations;

■Capability to understand the physical implementation and floorplan of the target SoC in order to generate a design that meets physical implementation requirements in terms of timing, area and power;

■Sophisticated design verification methodologies to ensure the quality of configurable interconnect IP across millions of possible combinations, as well as complex test benches for simulation and emulation;

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■In-depth knowledge of common interface protocols, graph theory, data models and graphical user interfaces;

■In-depth knowledge of safety standards including ISO 26262 ASIL B/D for automotive, IEEE 1685 IP-XACT IP standard for IP and SoC packaging, IEEE 1800 UVM verification standard; and

■Support a broad ecosystem of processors suppliers including Arm, RISC-V, x86, other IP vendors including Synopsys and Cadence, SoC design tool software providers, semiconductor foundries including TSMC and Intel Foundry, and others.

SoC integration automation development is similarly challenging as it requires broad support of the IP packaging standard, IEEE 1685 IP-XACT, and the ability to deliver features and enhancements required as customers deploy ever-changing IP block libraries for their SoC projects, address hardware-software integrations. Our SoC Integration Automation software solutions have to conform not only to industry standards, but also to ever-evolving SoC integration methodologies.

Once interconnect IP is designed into customer SoC projects, there are significant switching costs to adopting different interconnect IP and SoC Integration Automation software solutions, especially in the automotive sector and industrial applications, where switching interconnect IP solutions may involve product functional safety re-certification.

Our research and development strategy includes offering customers several product enhancement releases per year, complemented with a planned introduction of at least one new interconnect IP or SoC Integration Automation software product every year.

We believe we have assembled one of the premier engineering teams for interconnect IP development and SoC Integration Automation software in the world. As of December 31, 2025, we had 112 engineers devoted to interconnect IP development and 58 engineers devoted to SoC Integration Automation software solutions totaling 170 employees. In 2025, we spent $49.9 million on research and development, which represented 71% of our revenue.

Competition

For interconnect IP, we primarily compete with interconnect solutions developed internally by our SoC customers and potential customers. Many of the largest semiconductor companies have their own interconnect IP development teams which make customer penetration relatively difficult, time-consuming, and expensive. However, we believe that over time the expense and difficulty of developing a broad suite of interconnect IP and SoC integration automation has the potential to expand the use of commercial SoC integration solutions. In addition, we also compete with third-party providers, including Arm and several smaller companies. While we do compete with Arm in the interconnect IP market, we believe our solutions are complementary to Arm’s processor portfolio and protocol deployment and are actively collaborating on joint automotive solutions and integrate with Arm processor IPs. We often execute the integration of Arm processors in heterogeneous environments, which can accelerate the deployment of Arm processors. While smaller companies are developing interconnect solutions, we believe that our extensive investment in research and development over many years creates a barrier to entry. Developing interconnect IP solutions that are robust, configurable, and capable of handling multiple functionalities require deep technology expertise and large research and development investments. We compete based on die area reduction, lower idle power consumption, improved data movement performance such as frequency, latency, and bandwidth, as well as faster time to market. We believe we compete favorably with respect to these factors.

Based on management’s experience, we believe that in order to develop a new interconnect IP product, it would take a new entrant in the interconnect IP market three to four years to develop a mature product, two to four years of market development and five to seven years to build a royalty-generating customer base.

Our SoC Integration Automation software solutions similarly compete mainly against internally developed solutions. Commercial competitors consist of smaller companies that generally provide point products rather than complete solutions.

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Intellectual Property and Proprietary Rights

We rely on a combination of intellectual property rights, including patents, trade secrets, copyrights and trademarks, and contractual protections, to protect our core technology and intellectual property. As of December 31, 2025, we had 115 total allowed or issued patents, pending patent applications and non-expired provisional patent applications worldwide. Of these 115 allowed or issued patents, 88 are U.S. allowed or issued patents, 10 are China issued patents, six are South Korea issued patents, four are U.K. issued patents, four are Europe issued patents, and three are Japan issued patents. The 115 allowed or issued patents generally expire between July 2035 and June 2043. As of December 31, 2025, we had 146 pending non-provisional and provisional patent application filings, 62 in the United States, 28 in Europe, 24 in China, 13 in South Korea, 13 in Japan and six in the World Intellectual Property Organization. In addition, we have a trademark program covering, where feasible and in accordance with local laws, our products as well as our corporate names and logos.

Our progress in developing our technology and products, and our ability to compete worldwide, is a direct result of our commitment to develop and maintain leadership of our proprietary products and to develop and file to protect our intellectual property. We rely on a combination of patent, trademark, trade secret, and copyright laws, as well as contractual and licensing restrictions to protect the proprietary aspects of our technology. We also take steps to protect against misuse of our licensed products, for example with license keys that limit the time allowed for our licensee customers to use configuration tools to generate hardware description source code that is used in their semiconductor hardware products.

We routinely use non-disclosure agreements, limited evaluation agreements, and substantive license agreements with procedures to assist customer usage while limiting wrongful disclosure or misuse of our intellectual property. In addition, we are committed to developing products not only in the U.S. but in France, Poland, and other countries, where the country of origin may favorably impact the ability to license our IP solutions and technology in accordance with applicable export laws and regulations. Technological change and customer needs for emerging feature needs in our solutions inspire and motivate our personnel to update and enhance our offerings periodically.

We focus on patent protection beyond the United States in countries and jurisdictions where we determine that such filings will assist the strategic reach and value of our patent portfolio. Patents and other legal IP protections arise when we have conceived or developed novel and valuable new or improved technology relating to our IP solutions, that may affect our customer and our own licensing business outside the U.S. Certain countries in which our IP solutions are or may be developed, manufactured or sold may not have or enforce laws that protect our technology and intellectual property rights to the same extent as under U.S. law.

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Material Agreements

Qualcomm Agreements

In connection with an Asset Purchase Agreement by and among Qualcomm Technologies, Inc. and Qualcomm France SARL (collectively, Qualcomm) and us and certain of our subsidiaries dated October 9, 2013, pursuant to which we sold to Qualcomm certain assets and intellectual property related to our FlexNoC product (the Purchase Agreement), we and our affiliates retained a non-exclusive, worldwide, perpetual right under patents acquired under the Purchase Agreement to, among other things, manufacture, license and distribute certain FlexNoC products and certain modifications thereto (the Retained Rights). In addition, we and Qualcomm Technologies, Inc. entered into a License Agreement dated October 11, 2013 (the License Agreement) pursuant to which we and our affiliates obtained a license to, among other things, reproduce, use, license, and distribute certain FlexNoC-related works of authorship and technology that were acquired or owned by Qualcomm in connection with the Purchase Agreement for the purpose of enabling us to continue to offer and support FlexNoC products and certain modifications thereto (the Licensed Rights). There is no charge under the Purchase Agreement for our use of the Retained Rights or the Licensed Rights. Our rights in the Retained Rights continue until the last to expire of the relevant patents, and the License Agreement continues in perpetuity, in each case unless terminated as described below.

Qualcomm may terminate the Retained Rights in the event (i) we or our subsidiaries that are party to the Purchase Agreement breach any material terms of the Purchase Agreement applicable to the Retained Rights or any material terms of the License Agreement and fail to cure any such breach within 90 days after notice of such breach from Qualcomm, or (ii) we or any of our affiliates initiate a claim of patent infringement against Qualcomm or its affiliates (excluding such claims that are counterclaims in proceedings initiated by Qualcomm or its affiliates) and does not withdraw such claim within 30 days after Qualcomm’s written request to do so. Qualcomm may terminate the License Agreement in the event we breach any material terms of the License Agreement or any material terms of the Purchase Agreement applicable to the Retained Rights and fail to cure such breach within 90 days after notice of such breach from Qualcomm. Qualcomm may also terminate rights granted under the License Agreement to a certain development environment used in connection with our FlexNoC product (which could effectively preclude us from continuing to enhance our FlexNoC product and adversely affect our FlexNoC business) in the event of a change of control of our company (as defined in the License Agreement) which would effectively include, in a transaction or series of related transactions, a sale of our company, or the sales of securities by us or our stockholders that would result in the stockholders and option holders of our company as of the date of the License Agreement not retaining beneficial ownership of more than 50% of our company. We believe that, as we have and continue to deliver new products since the date of the License Agreement, such as our range of SoC Integration Automation software solutions, Ncore cache coherent interconnect, CodaCache last-level cache, and CSRCompiler physical awareness capabilities, the importance to our business and product portfolio of the FlexNoC development environment will decrease over time.

We may not assign the License Agreement without Qualcomm’s written consent (and a change of control of our company shall be considered an assignment for the purposes of such prohibition) except that we may assign the License Agreement to an acquirer of our business that consists of licensing certain FlexNoC products, and we may only assign the Retained Rights to an entity to whom we have assigned the License Agreement.

Governmental Regulation

We are subject to regulation by various governmental agencies in the United States and other jurisdictions in which we operate. These laws and regulations (and the government entities, regulators, and agencies responsible for their enforcement) in the United States cover among other things: radio frequency emission regulatory activities (Federal Communications Commission); anti-trust regulatory activities (Federal Trade Commission and Department of Justice); insider trading, anti-bribery, and anti-corruption (Department of Justice), consumer protection (Federal Trade Commission); import/export regulatory activities (Department of Commerce and Department of Treasury); product safety regulatory activities (Consumer Products Safety Commission); worker safety (Occupational Safety and Health Administration); environmental protection (Environmental Protection Agency and similar state and local agencies); employment matters (Equal Employment Opportunity Commission); and federal and state tax and other regulations by a variety of regulatory authorities in each of the areas in which we conduct business. Our operations are also subject to the U.S. Foreign Corrupt Practices Act of 1977, as amended (the FCPA), the U.S. domestic bribery statute contained in 18 U.S.C. § 201, the U.S. Travel Act, the USA PATRIOT Act, as well as the anti-corruption, anti-bribery, and anti-money laundering laws in the U.S. and other countries where we conduct business.

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In addition, certain of our products, including our IP interconnect and other solutions and technology, are subject to U.S. export controls, including the U.S. Department of Commerce’s Export Administration Regulations (EAR) and economic and trade sanctions regulations administered by the U.S. Treasury Department’s Office of Foreign Assets Controls (OFAC). Other products are subject to French export controls. These regulations may limit the export of our products and technology, and the provision of our services outside of the United States and/or France, or may require export authorizations, including by license, a license exception, or other appropriate government authorizations and conditions, including annual or semi-annual reporting. Export control and economic sanctions laws may also include prohibitions on the sale or supply of certain of our products to embargoed or sanctioned countries, regions, governments, persons, and entities. The export and re-export of our products and technology and the provision of services, including by our partners, must comply with these laws, or else we may be adversely affected through reputational harm, government investigations, penalties, and a denial or curtailment of our ability to export our products and technology. With respect to government authorizations, we have no pending export license requests to the U.S. Department of Commerce's Bureau of Industry and Security (BIS) or any other government agency, and no export licenses are currently required to export our products from the United States or other countries to countries where we do business.

Complying with export control and sanctions laws may be time-consuming and may result in the delay or loss of sales opportunities. Although we take precautions to prevent our products and technology from being provided in violation of such laws, our products and technology have previously been, and could in the future be, provided inadvertently in violation of such laws, despite the precautions we take. If we are found to be in violation of U.S. sanctions or export control laws, it could result in substantial fines and penalties for us and the individuals working for us. Changes in export or import laws or sanctions policies may adversely impact our operations, delay the introduction and sale of our products in international markets, or, in some cases, prevent the export or import of our products and technology to certain countries, regions, governments, persons, or entities altogether, which could harm our business.

From time to time, we have adopted and will continue to adopt remedial measures in response to government regulation. For example, we have adopted several remedial measures prior to, in connection with and following the initial notification of voluntary self-disclosure we submitted to BIS. These compliance enhancements were developed and implemented in consultation with outside counsel specializing in U.S. trade compliance. These steps have included annual basic export compliance training within our company, updating our written export control policies and procedures, and adopting a revised export compliance manual in 2021. We have provided export awareness training for relevant personnel including in 2023 and 2022. We previously provided our sales employees worldwide with training in basic export compliance. We engaged third-party vendor software to assist us with an ongoing screening of new and existing customers, third-party agents or representatives, suppliers, and other vendors against U.S., France and several other jurisdictions prohibited or restricted party lists. We screen all customers against applicable lists of denied or restricted parties, including the Entity List administered by BIS as well as the list of Specially Designated Nationals and Blocked Persons, administered by the Treasury Department’s Office of Foreign Assets Control.

For a discussion of the various risks we face from regulation and compliance matters, see “Risk Factors—Risks Related to Our Business and Industry—We are subject to data protection, AI, and privacy and security laws, regulations, standards and other requirements across different markets where we conduct our business. Our actual or perceived failure to comply with such obligations could harm our business,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—Our failure to comply with the large body of laws and regulations to which we are subject could materially harm our business,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—Our failure to comply with the Foreign Corrupt Practices Act, other applicable anti-corruption and anti-bribery laws, and applicable anti-money laundering laws could subject us to penalties and other adverse consequences,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—We are subject to government regulations, including import, export and economic sanctions laws and artificial intelligence regulations that may restrict our ability to sell to or get paid by customers in certain regions, or expose us to liability and increase our costs,” “Risk Factors—Risks Related to Legal, Regulatory, Accounting and Tax Matters—We will lose sales if we are unable to obtain government authorization to export certain of our products and services, and we will be subject to legal and regulatory consequences if we do not comply with applicable export control laws and regulations or if such laws and regulations were to change.”

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Human Capital Resources

As of December 31, 2025, we had 299 employees as follows:

We consider relations with our employees to be good and have never experienced a work stoppage. None of our employees are either represented by a labor union, although our employees in France are subject to a collective bargaining agreement.

Our human capital resources objectives include, as applicable, identifying, recruiting, retaining, incentivizing and integrating our existing and additional employees. The principal purposes of our equity incentive plans are to attract, retain and motivate selected employees, consultants and directors through the granting of stock-based compensation awards and cash-based performance bonus awards.

Corporation Information

We were incorporated in the State of Delaware in April 2004. Our principal executive offices are located at 900 E. Hamilton Ave. Suite 300, Campbell, CA 95008. Our telephone number is (408) 470-7300, and our website address is www.arteris.com. The information contained on, or that can be accessed through, our website is not incorporated by reference in this report and does not form a part of this report. You should not consider the information contained on our website to be part of this report in deciding whether to purchase shares of our common stock. Our common stock is traded on the Nasdaq Stock Market under the symbol “AIP”.

Available Information

Our website address is www.arteris.com. Information found on, or accessible through, our website is not a part of, and is not incorporated into, this Annual Report on Form 10-K. We file electronically with the SEC our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act. We make available on our website at www.arteris.com, free of charge, copies of these reports and other information as soon as reasonably practicable after we electronically file such material with, or furnish it to, the SEC.